The present invention relates to digital video signal recording and reproducing devices and transmission devices, and more particularly to a digital video signal recording and reproducing device which compresses a digital video signal and records it on a recording medium, and which reads the recorded signal and reproduces it, and to a digital video signal transmission device which compresses a digital video signal and transmits it through a transmission medium.
Recently, in the field of TV broadcasts, a video signal can be recorded or transmitted in digitized form. At present, the standard-definition television broadcasts mainly use a digital video signal with 480 effective lines and the high-definition television (HDTV) broadcasts mainly use a digital video signal with 1080 effective lines.
Conventional digital video signal recording and reproducing devices for recording and reproducing digital video signals include digital VCRs (Digital Video Cassette Recorders, as D3, D5, etc.), which adopt magnetic tapes (video casettes) as the recording medium. Recently, a standard about consumer-use digital VCRs using very small-sized video cassettes has been formulated (DV standard) and some new products based on the standard have been introduced.
While the DV standards were originally targeted at the standard-definition television broadcasts, they were expanded to the HDTV broadcast later. That is to say, the current DV standards define a compression/recording system about the digital video signal used in the standard-definition television broadcasts (hereinafter referred to as SD) and a compression/recording system for the digital video signal used in the HDTV broadcast (hereinafter referred to as HD).
In the case of SD, the image format of the digital video signal (which is referred to as SD format) uses 480 effective lines for both of luminance and color difference, 720 pixels of horizontal effective samples for luminance and 180 pixels for color difference (4:1:1). In the case of HD, the image format of the digital video signal (which is referred to as HD format) uses 1024 effective lines for luminance and 512 lines for color difference, and 1008 pixels of horizontal effective samples for luminance and 336 pixels for color difference (3:1:0).
A conventional digital video signal recording and reproducing device according to the DV standard  less than HD greater than  is now described.
FIG. 19 is a block diagram showing the entire structure of the conventional digital video signal recording and reproducing device according to the DV standard  less than HD greater than .
In FIG. 19, the conventional digital video signal recording and reproducing device according to the DV standard (hereinafter referred to as conventional DV-VCR  less than HD greater than ) has a compression circuit 170, a recording circuit 171, a recording medium 172, a reproducing circuit 173, and a decoding circuit 174.
It is assumed here that a digital video signal for HDTV broadcast  less than studio standard greater than  is inputted to the conventional DV-VCR  less than HD greater than . Its image format uses 1080 effective lines for both of luminance and color difference, 1920 pixels of horizontal effective samples for luminance and 960 pixels for color difference (4:2:2). The recording medium 172 is a magnetic tape.
FIG. 20 is a block diagram showing the structure of the compression circuit 170 of FIG. 19.
In FIG. 20, the compression circuit 170 has a filter circuit 180, a macro block assembling circuit (DV) 181, a shuffling circuit 182, a DCT circuit (DV) 183, a quantization circuit (DV) 184, a zigzag scan circuit (DV) 185, a variable-length encoding circuit (DV) 186, a DCT mode decision circuit 187, and a code rate control circuit 188.
The character xe2x80x9c(DV)xe2x80x9d indicates a circuit which operates according to the DV standard (which applies hereinafter).
The filter circuit 180 converts the image format of the input digital video signal. The macro block assembling circuit (DV) 181 assembles macro blocks from the output signal of the filter circuit 180. The shuffling circuit 182 shuffles the output signal of the macro block assembling circuit (DV) 181. The DCT circuit (DV) 183 applies DCT (Discrete Cosine Transform) to the output signal of the shuffling circuit 182. The quantization circuit (DV) 184 quantizes the output signal of the DCT circuit (DV) 183. The zigzag scan circuit (DV) 185 zigzag-scans the output signal of the quantization circuit (DV) 184. The variable-length encoding circuit (DV) 186 variable-length encodes the output signal of the zigzag scan circuit (DV) 185.
The DCT mode decision circuit 187 decides whether the DCT should be the 8-8DCT or the 2-4-8DCT defined by the DV standard  less than HD greater than . The code rate control circuit 188 controls the code rate of the output of the quantization circuit (DV) 184.
Referring to FIG. 19 again, the recording circuit 171 records the output signal of the compression circuit 170 on the magnetic tape. In this process, the recording circuit 171 writes one frame in a region of a predetermined size (20 tracks).
The reproducing circuit 173 reproduces the digital video signal recorded on the magnetic tape.
FIG. 21 is a block diagram showing the structure of the decoding circuit 174 of FIG. 19.
In FIG. 21, the decoding circuit 174 has a variable-length decoding circuit (DV) 190, a zigzag scan circuit (DV) 191, an inverse quantization circuit (DV) 192, an inverse DCT circuit (DV) 193, a de-shuffling circuit 194, a reverse macro block assembling circuit (DV) 195, and a filter circuit 196.
The variable-length decoding circuit (DV) 190 variable-length decodes the output signal of the reproducing circuit 173. The zigzag scan circuit (DV) 191 zigzag-scans the output signal of the variable-length decoding circuit (DV) 190. The inverse quantization circuit (DV) 192 applies inverse quantization to the output signal of the zigzag scan circuit (DV) 191. The inverse DCT circuit (DV) 193 applies inverse DCT to the output signal of the inverse quantization circuit (DV) 192. The de-shuffling circuit 194 de-shuffles the output signal of the inverse DCT circuit (DV) 193. The reverse macro block assembling circuit (DV) 195 assembles a digital video signal from the output signal (macro blocks) of the de-shuffling circuit 194. The filter circuit 196 reversely converts the image format of the output signal of the reverse macro block assembling circuit (DV) 195.
Operation of this conventional DV-VCR  less than HD greater than  is now described.
In FIG. 19, a digital video signal is inputted to the compression circuit 170.
In the compression circuit 170 of FIG. 20, first, the filter circuit 180 converts the image format of the input digital video signal from the HDTV broadcast  less than studio standard greater than  to the DV standard  less than HD greater than  (i.e. HD format). Next, the macro block assembling circuit (DV) 181 assembles macro blocks from the output signal of the filter circuit 180.
The operation of the macro block assembling circuit (DV) 181 is now described referring to FIG. 22.
FIG. 22 is a diagram in assistance of explaining the process in which the macro block assembling circuit (DV) 181 of FIG. 20 assembles macro blocks from the output signal of the filter circuit 180, i.e. from the digital video signal (HD format).
In FIG. 22, the digital video signal (HD format) is composed of a luminance signal (Y) with 1008 pixels*1024 lines and two color difference signals (Pb, Pr) with 336 pixels*512 lines.
The macro block assembling circuit (DV) 181 extracts 3*2=6 blocks as a unit from the luminance signal (i.e. adjacent 6 blocks including horizontal 3 blocks and vertical 2 blocks), where each block consisting of 8 pixels*8 lines. It also extracts one block composed of 8 pixels*8 lines from each of the two color difference signals. 8 blocks extracted as such are handled as one macro block (in the diagram, the macro block xe2x80x9c0xe2x80x9d).
The macro block assembling circuit (DV) 181 thus assembles 2688 macro blocks from one frame of the digital video signal (HD format). 12 dummy macro blocks are added to each frame, and the macro block assembling circuit (DV) 181 thus outputs 2700 macro blocks per frame.
Next, Referring to FIG. 20 again, the shuffling circuit 182 shuffles the output signal of the macro block assembling circuit (DV) 181. FIG. 23 shows an example of an input to and an output from the shuffling circuit 182 of FIG. 20.
Next, the DCT mode decision circuit 187 refers to the output signal of the shuffling circuit 182 and decides, for each block, whether to apply 8-8DCT or 2-4-8DCT as DCT. It then informs the DCT circuit (DV) 183 of the result (DCT mode information). In response to the information, the DCT circuit (DV) 183 applies 8-8DCT or 2-4-8DCT to the output signal of the shuffling circuit 182.
Next, the code rate control circuit 188 estimates the code rate for every 5 macro blocks which will be outputted from the quantization circuit (DV) 184 on the basis of the output signal of the DCT circuit (DV) 183 and controls the code rate so that 5 macro blocks can be accommodated in 5 sync blocks (i.e. it gives quantization information for code rate control to the quantization circuit (DV) 184). In response, the quantization circuit (DV) 184 quantizes the output signal of the DCT circuit (DV) 183.
Next, the zigzag scan circuit (DV) 185 zigzag-scans the output signal of the quantization circuit (DV) 184. Next, the variable-length encoding circuit (DV) 186 variable-length encodes the output signal of the zigzag scan circuit (DV) 185.
The DCT mode information outputted from the DCT mode decision circuit 187 and the quantization information outputted from the code rate control circuit 188 are given to the recording circuit 171 together with the variable-length code outputted from the variable-length encoding circuit (DV) 186. The DCT mode information and the quantization information are of fixed length.
In FIG. 19, the recording circuit 171 records the output signal of the compression circuit 170 on the magnetic tape (the variable-length code, DCT mode information, and quantization information). In this process, the recording circuit 171 writes one frame of signal (2700 macro blocks) in a region of a predetermined size (20 tracks=2700 sync blocks).
The operation of this recording circuit 171 is now described referring to FIG. 24.
FIG. 24 is a diagram used to explain the operation of the recording circuit 171 of FIG. 19.
In FIG. 24, the recording circuit 171 receives the variable-length code (8 blocks) outputted from the variable-length encoding circuit (DV) 186, the DCT mode information outputted from the DCT mode decision circuit 187, and the quantization information outputted from the code rate control circuit 188; the recording circuit 171 receives 5 macro blocks as a unit (1 macro block=8 blocks).
When recording the variable-length code, DCT mode information and quantization information on the magnetic tape, the recording circuit 171 records 5 macro blocks in 5 synch blocks.
That is to say, a synch block consists of a region for storing the quantization information (1 byte) and a region for storing the DCT mode information and variable-length code (76 bytes). The latter region is divided into a total of 8 regions including six 10-byte regions for luminance blocks and two 8-byte regions for color difference blocks. As shown in FIG. 8 {circle around (1)} to {circle around (3)}, the recording circuit 171 first stores the quantization information and the DCT mode information in the sync block ({circle around (1)}) and next stores the variable-length code.
When storing the variable-length code, the recording circuit 171 stores 8 blocks forming 1 macro block respectively into the 8 regions mentioned above. In this process, for luminance blocks exceeding 10 bytes and color difference blocks exceeding 8 bytes, the 10 bytes or 8 bytes are stored first ({circle around (2)}). The remainders are sequentially stored in blanks in regions where a luminance block smaller than 10 bytes or a color difference block smaller than 8 bytes was stored ({circle around (3)}).
The processes {circle around (1)} to {circle around (3)} are performed for each macro block. In this process, some macro blocks may be left unstored in the sync blocks or some sync blocks may be left unfilled. Accordingly, after repeating the processes {circle around (1)} to {circle around (3)} five times, the recording circuit 171 sequentially stores the parts of the 5 macro blocks which are left unstored into blanks in other sync blocks ({circle around (4)}).
Referring to FIG. 19 again, the reproducing circuit 173 reproduces the digital video signal recorded on the magnetic tape. The output signal of the reproducing circuit 173 (the variable-length code, DCT mode information, and quantization information) is inputted to the decoding circuit 174.
In the decoding circuit 174 of FIG. 21, first, the variable-length decoding circuit (DV) 190 variable-length decodes the output signal of the reproducing circuit 173 (the variable-length code). Next, the zigzag scan circuit (DV) 191 zigzag-scans the output signal of the variable-length decoding circuit (DV) 190. Next, the inverse quantization circuit (DV) 192 applies inverse quantization to the output signal of the zigzag scan circuit (DV) 191 on the basis of the output signal of the reproducing circuit 173 (the quantization information). Next, the inverse DCT circuit (DV) 193 applies inverse DCT to the output signal of the inverse quantization circuit (DV) 192 on the basis of the output signal of the reproducing circuit 173 (the DCT mode information). Next, the de-shuffling circuit 194 de-shuffles the output signal of the inverse DCT circuit (DV) 193.
Next, the reverse macro block assembling circuit (DV) 195 assembles a digital video signal from the output signal (macro blocks) of the de-shuffling circuit 194. That is to say, it performs operation reverse to that performed by the macro block assembling circuit (DV) 181 on the recording side.
More specifically, in FIG. 22, it assembles a digital video signal (HD format) composed of a luminance signal (Y) with 1008 pixels*1024 lines and two color difference signals (Pb, Pr) with 336 pixels*512 lines from the macro blocks given from the de-shuffling circuit 194.
Next, the filter circuit 196 reversely converts the image format of the output signal of the reverse macro block assembling circuit (DV) 195 from HD to HDTV broadcast  less than studio standard greater than .
As described above, the conventional DV-VCR  less than HD greater than  converts the image format of a digital video signal for HDTV broadcasting  less than studio standard greater than  into HD format and then compresses, records and reproduces the signal according to the DV standard  less than HD greater than .
Another conventional digital video signal recording and reproducing device according to the DV standard  less than SD greater than  (hereinafter referred to as conventional DV-VCR  less than SD greater than ; not shown) for recording and reproducing a digital video signal for the standard-definition television broadcasts has a similar structure to that shown in FIG. 19.
The conventional DV-VCR  less than SD greater than  operates in basically the same way as the conventional DV-VCR  less than HD greater than  described above. However, due to the difference in image format, the process for assembling macro blocks differs from that of the conventional DV-VCR  less than HD greater than . Hence, the process of assembling macro blocks from a digital video signal based on the standard-definition television broadcasts (SD format) is now described.
FIG. 25 is a diagram used to explain the process in which a macro block assembling circuit (not shown) in the conventional digital video signal recording and reproducing device based on the DV standard  less than SD greater than  (conventional DV-VCR  less than SD greater than ) assembles macro blocks from a digital video signal (SD format).
In FIG. 25, the digital video signal (SD format) is composed of a luminance signal (Y) with 720 pixels*480 lines and two color difference signals (Pb, Pr) with 180 pixels*480 lines.
The macro block assembling circuit first divides the luminance signal into 704 pixels on the left and 16 pixels on the right and divides each color difference signal into 176 pixels on the left and 4 pixels on the right.
Next, the macro block assembling circuit applies the following processing to the left 704 pixels of the luminance signal and the left 176 pixels of the color difference signals. That is to say, it extracts 4*1=4 blocks as a unit from the luminance signal, where each block consisting of 8 pixels*8 lines. It also extracts one block of 8 pixels*8 lines from each of the two color difference signals. The extracted 6 blocks are handled as one macro block (in the drawing the macro block xe2x80x9c0xe2x80x9d).
Next, the macro block assembling circuit applies the following processing to the right 16 pixels of the luminance signal and the right 4 pixels of the color difference signals. That is to say, it extracts 2*2=4 blocks as a unit from the luminance signal, where each block consisting of 8 pixels*8 lines. It also extracts one block consisting of 4 pixels*16 lines from each of the two color difference signals. The extracted 6 blocks are handled as one macro block (in the drawing the macro block xe2x80x9cNxe2x80x9d).
Accordingly, in the conventional DV-VCR  less than SD greater than , the macro block assembling circuit assembles 1350 macro blocks from one frame of the digital video signal (SD format).
In this process, the recording circuit provided in the conventional DV-VCR  less than SD greater than  writes one frame of signal (1350 macro blocks) in 10 tracks (=1350 sync blocks). Aside from the difference in recording rate, the operation of the recording circuit in the DV-VCR  less than SD greater than  is the same as that of the recording circuit 171 in the DV-VCR  less than HD greater than  (see FIG. 24).
By the way, widespread digital video signal compression systems include the MPEG system as well as the DV system, and some broadcasting devices are hence constructed to directly receive an MPEG stream as input (e.g. equipment for CS broadcasts etc.). Accordingly there is a demand for digital video signal recording and reproducing devices in which the reproducing side can extract not only a digital video signal but also an MPEG stream. However such devices are not conventionally available.
The method below may be employed to realize a digital video signal recording and reproducing device which can extract an MPEG stream on the reproducing side. This method uses the above-described DV-VCR and an existing MPEG encoder. This method is now described referring to FIG. 26.
FIG. 26 is a block diagram showing the whole structure of the digital video signal recording and reproducing device which can extract an MPEG stream on the reproducing side; it uses the DV-VCR of FIG. 19 and the existing MPEG encoder.
In FIG. 26, the digital video signal recording and reproducing device which can extract an MPEG stream on the reproducing side (which is referred to as conventional digital video signal recording and reproducing device hereinafter) has the DV-VCR and MPEG encoder.
It is assumed here that a digital video signal for HDTV broadcast  less than studio standard greater than  is inputted to the conventional digital video signal recording and reproducing device. The recording medium 172 is a magnetic tape.
The DV-VCR is the same as that shown in FIG. 19. The MPEG encoder includes a compression circuit 240.
FIG. 27 is a block diagram showing the structure of the compression circuit 240 of FIG. 26 (that in the MPEG encoder).
In FIG. 27, the compression circuit 240 has a macro block assembling circuit (MPEG) 250, a DCT circuit (MPEG) 251, a quantization circuit (MPEG) 252, a zigzag scan circuit (MPEG) 253, a variable-length encoding circuit (MPEG) 254, an MPEG syntax circuit 255, a DCT mode decision circuit 256, and a code rate control circuit 257.
The character xe2x80x9c(MPEG)xe2x80x9d indicates a circuit which operates according to the MPEG standard (the same applies hereinafter).
The macro block assembling circuit (MPEG) 250 assembles macro blocks from the output signal of the DV-VCR. The DCT circuit (MPEG) 251 applies DCT to the output signal of the macro block assembling circuit (MPEG) 250. The quantization circuit (MPEG) 252 quantizes the output signal of the DCT circuit (MPEG) 251. The zigzag scan circuit (MPEG) 253 zigzag-scans the output signal of the quantization circuit (MPEG) 252. The variable-length encoding circuit (MPEG) 254 variable-length encodes the output signal of the zigzag scan circuit (MPEG) 253. The MPEG syntax circuit 255 converts the output signal of the variable-length encoding circuit (MPEG) 254 into a stream based on the MPEG syntax. The DCT mode decision circuit 256 decides whether to perform frame DCT or field DCT defined by the MPEG standard. The code rate control circuit 257 controls the code rate outputted from the quantization circuit (MPEG) 252.
Operation of this conventional digital video signal recording and reproducing device is now described.
In FIG. 26, first, a digital video signal is inputted to the DV-VCR. The DV-VCR compresses the input signal and records it on the recording medium 172, and then reproduces and decodes the signal recorded on the recording medium 172 to output a digital video signal. This output signal is inputted to the MPEG encoder.
In the compression circuit 240 of the MPEG encoder shown in FIG. 27, first, the macro block assembling circuit (MPEG) 250 assembles macro blocks from the output signal of the DV-VCR. The DCT mode decision circuit 256 refers to the output signal of the macro block assembling circuit (MPEG) 250 to decide for each macro block whether to perform frame DCT or field DCT defined by the MPEG standard and informs the DCT circuit (MPEG) 251 of the result (DCT mode information). According to the information, the DCT circuit (MPEG) 251 applies frame DCT or field DCT to the output signal of the macro block assembling circuit (MPEG) 250.
Next, the code rate control circuit 257 estimates the code rate of the MPEG stream output (from the compression circuit 240) on the basis of the output signal of the DCT circuit (MPEG) 251 and controls the code rate so that the MPEG stream falls within a given code rate (that is to say, it gives quantization information for the code rate control to the quantization circuit (MPEG) 252). In response, the quantization circuit (MPEG) 252 quantizes the output signal of the DCT circuit (MPEG) 251. Next, the zigzag scan circuit (MPEG) 253 zigzag-scans the output signal of the quantization circuit (MPEG) 252. Next the variable-length encoding circuit (MPEG) 254 variable-length encodes the output signal of the zigzag scan circuit (MPEG) 253. Next the MPEG syntax circuit 255 converts the output signal of the variable-length encoding circuit (MPEG) 254, the output signal of the DCT mode decision circuit (DCT mode information), and the output signal of the code rate control circuit (quantization information) into a stream based on the MPEG syntax.
In this way, in the conventional digital video signal recording and reproducing device including an MPEG encoder connected to the DV-VCR, the output signal of the DV-VCR, i.e., a digital video signal once DV compressed and recorded and then reproduced and decoded, is MPEG compressed through the MPEG encoder, thereby an MPEG stream is obtained on the reproducing side.
As another method, it is supposed that an MPEG stream can be extracted on the reproducing side by compressing a digital video signal by MPEG in the first step and recording it on a magnetic tape.
However, as for the device of FIG. 26, its circuit configuration must be complex and the quality of the image obtained from the extracted MPEG stream will be considerably deteriorated, since it performs the MPEG compression after DV compression and decoding.
In addition, it is difficult to convert a DV stream (i.e. the output signal of the reproducing circuit 173) directly into an MPEG stream without once decoding it, since the DV standard (whether SD or HD) and the MPEG standard adopt different image formats.
For the image formats, the DV standard uses (4:1:1) for SD and (3:1:0) for HD. The MPEG standard uses (4:4:4), (4:2:2), or (4:2:0) (the above-described MPEG encoder adopts (4:2:2)).
On the other hand, a device which compresses a digital video signal by MPEG and records it has the following problem. In MPEG compression, the redundancy of the signal may be increased depending on the number of effective lines of the digital video signal (that is, the encoding efficiency is reduced), which results in wasteful consumption of the capacity of the recording medium 172.
This increase in redundancy occurs when assembling macro blocks according to the MPEG standard from a digital video signal in which the number of effective lines is not a multiple of 16. Such case is now exemplarily described referring to FIGS. 28 and 29. In the example, macro blocks are assembled according to the MPEG standard from a digital video signal for HDTV broadcast  less than studio standard greater than  with 1080 effective lines.
FIGS. 28 and 29 are diagrams used to explain the process for assembling macro blocks according to the MPEG standard from an HDTV broadcast digital video signal  less than studio standard greater than .
In FIGS. 28 and 29, the digital video signal is an HDTV broadcast  less than studio standard greater than  signal composed of a luminance signal (Y) with 1920 pixels*1080 lines and two color difference signals (Pb, Pr) with 960 pixels*1080 lines. In the luminance signal and the two color difference signals, 8 pixels*8 lines form one block.
First, as shown in FIG. 28, the number of effective lines of the digital video signal is increased from 1080 lines to 1088 lines. That is to say, dummy blocks of 8 lines are added to (the screen bottoms of) the luminance signal and the two color difference signals (i.e. 240*1 dummy blocks are added to the luminance signal and 120*1 to each of the two color difference signals).
Next, as shown in FIG. 29, macro blocks are assembled from the digital video signal having the increased effective lines (1088 effective lines). That is to say, 2*2=4 blocks are extracted as a unit from the enlarged luminance signal and 1*2=2 blocks from each of the two enlarged color difference signals, where the extracted 8 blocks are handled as one macro block (in the drawing the macro block xe2x80x9c0xe2x80x9d).
In this way, when assembling macro blocks according to the MPEG standard from a digital video signal in which the number of effective lines is not a multiple of 16, the number of effective lines is increased to a multiple of 16, i.e. an appropriate number of dummy blocks are added to the signal. These dummy blocks increase the signal redundancy.
The problem above also exists in digital video signal transmission devices which compress a digital video signal and transmit it through a transmission medium so that the receiving end can extract an MPEG stream.
That is to say, when a digital video signal is DV-compressed and transmitted, and the receiving end decompresses it and compresses it again by MPEG, complex processing circuitry is required and the image quality is considerably deteriorated. On the other hand, when a digital video signal is compressed by MPEG in the first step and transmitted, the signal redundancy is increased depending on the number of effective lines to wastefully consume the band of the transmission medium.
Accordingly, an object of the present invention is to provide a digital video signal recording and reproducing device in which, when recording and reproducing a digital video signal in which the number of effective lines is not a multiple of 16, the reproducing side can extract an MPEG stream with a simple structure and without suffering noticeable image quality deterioration, and without wastefully consuming the capacity of the recording medium.
Another object of the present invention is to provide a digital video signal transmission device in which, when transmitting a digital video signal in which the number of effective lines is not a multiple of 16, the receiving end can extract an MPEG stream with a simple structure and without suffering noticeable image quality deterioration, and without wastefully consuming the band of the transmitting medium.
The present invention has the following features to solve the problems described above.
A first aspect of the present invention is directed to a digital video signal recording device for recording a digital video signal in which the remainder left when the number of its effective lines is divided by 16 is not less than 1 and not more than 8, the device comprising:
compressing means for compressing the digital video signal according to a procedure which partially differs from an MPEG standard; and
recording means for recording an output signal of the compressing means on a recording medium,
the compressing means comprising,
macro block assembling means for adding dummy lines of 7 lines maximum to the effective lines of the digital video signal and assembling macro blocks with 16 lines and macro blocks with 8 lines, and
DCT means for applying field DCT (Discrete Cosine Transform; which applies hereinafter) or frame DCT defined by the MPEG standard to the macro blocks with 16 lines and applying only the frame DCT defined by the MPEG standard to the macro blocks with 8 lines.
In accordance with the first aspect (and the second aspect below), in the process of compression, dummy lines of 7 lines maximum are added to a digital video signal in which the remainder left when the number of effective lines is divided by 16 is between 1 and 8 so that the remainder becomes 8 (note that no dummy line is added when the 16""s remainder of the number of effective lines is 8, e.g. when the number of effective lines is 1080), and macro blocks with 16 lines and macro blocks with 8 lines are assembled. The macro blocks with 8 lines are subjected only to the frame DCT defined by the MPEG standard. Accordingly, when reproducing the signal recorded on the recording medium and converting it into an MPEG stream, the macro blocks can be reassembled into those equivalent to macro blocks obtained by performing the process of increasing the number of lines as defined by the MPEG standard just by adding dummy blocks with 8 lines to the 8-line macro blocks.
Recording the digital video signal in this way eliminates the need to record dummy blocks with 8 lines on the recording medium (that is to say, as compared with a process of recording macro blocks equivalent to those obtained by performing the process of increasing the number of lines defined by the MPEG standard, the capacity of the recording medium corresponding to dummy blocks with 8 lines can be saved). Furthermore, in the process of reproduction, the macro blocks can be reassembled into macro blocks equivalent to those obtained by performing the process of increasing the number of lines defined by the MPEG standard just by adding dummy blocks with 8 lines, without the need to once convert the 8-line macro blocks into the digital video signal (that is, this saves the process of once converting the 8-line macro blocks back into the digital video signal and also alleviates the deterioration of the image quality).
Thus, the reproducing side can extract an MPEG stream with a simple structure and without causing noticeable deterioration of the image quality, and without wastefully consuming the capacity of the recording medium.
A second aspect is directed to a digital video signal recording and reproducing device for recording and reproducing a digital video signal in which the remainder left when the number of its effective lines is divided by 16 is not less than 1 and not more than 8, the device comprising:
compressing means for compressing the digital video signal according to a procedure which partially differs from an MPEG standard;
recording means for recording an output signal of the compressing means on a recording medium;
reproducing means for reproducing the signal recorded on the recording medium; and
converting means for converting an output signal of the reproducing means into an MPEG stream,
the compressing means comprising,
macro block assembling means for adding dummy lines of 7 lines maximum to the effective lines of the digital video signal and assembling macro blocks with 16 lines and macro blocks with 8 lines, and
DCT means for applying field DCT (Discrete Cosine Transform; which applies hereinafter) or frame DCT defined by the MPEG standard to the macro blocks with 16 lines and applying only the frame DCT defined by the MPEG standard to the macro blocks with 8 lines, and
the converting means comprising macro block reassembling means for reassembling the macro blocks assembled by the macro block assembling means into macro blocks which are equivalent to those obtained by performing a process of increasing the number of effective lines as defined by the MPEG standard.
According to a third aspect, in the second aspect,
the process of increasing the number of effective lines is a process of, when assembling macro blocks, adding dummy blocks to a digital video signal in which the number of effective lines is not a multiple of 16 to make the number of effective lines a multiple of 16, and
the macro block reassembling means adds dummy blocks with 8 lines to the macro blocks assembled by the macro block assembling means to reassemble the macro blocks equivalent to those obtained by performing the process of increasing the number of lines.
According to a fourth aspect, in the second aspect,
the compressing means further comprises,
encoding means for quantizing and variable-length encoding an output signal of the DCT means according to the procedure which partially differs from the MPEG standard, and
code rate control means for generating quantization information for controlling the code rate of the macro blocks assembled by the macro block assembling means so that N (N is an arbitrary natural number; which applies thereinafter) of the macro blocks can be exactly, without any remainder nor shortage stored in N fixed-length sync blocks, and
the recording means records the output signal of the compressing means on the recording medium in such a manner that one frame of the output signal is stored in a given number of fixed-length sync blocks on the recording medium.
According to a fifth aspect, in the second aspect,
the compressing means further comprises,
quantization means for quantizing an output signal of the DCT means according to the MPEG standard,
variable-length encoding means for variable-length encoding an output signal of the quantization means according to the MPEG standard, and
code rate control means for generating quantization information for controlling the code rate of the macro blocks assembled by the macro block assembling means so that N (N is an arbitrary natural number; which applies thereinafter) of the macro blocks can be exactly, without any remainder nor shortage, stored in N fixed-length sync blocks,
the converting means further comprises variable-length decoding means for variable-length decoding an output signal of the variable-length encoding means according to the MPEG standard and outputting a signal obtained by this process to the macro block reassembling means, and
the code rate control means generates the quantization information on the basis of the output signal of the DCT means and provides the quantization information to the quantization means.
According to a sixth aspect, in the second aspect,
the compressing means further comprises,
quantization means for quantizing an output signal of the DCT means according to the MPEG standard,
DV variable-length encoding means for variable-length encoding an output signal of the quantization means according to a DV standard, and
code rate control means for generating quantization information for controlling the code rate of the macro blocks assembled by the macro block assembling means so that N (N is an arbitrary natural number; which applies thereinafter) of the macro blocks can be exactly, without any remainder nor shortage, stored in N fixed-length sync blocks,
the converting means further comprises,
DV variable-length decoding means for variable-length decoding an output signal of the DV variable-length encoding means according to the DV standard and outputting a signal obtained by this process to the macro block reassembling means, and
MPEG variable-length encoding means for variable-length encoding an output signal of the macro block reassembling means according to the MPEG standard, and
the code rate control means generates the quantization information on the basis of the output signal of the DCT means and provides the quantization information to the quantization means.
In accordance with the sixth aspect, the device performs DV variable-length encoding in the process of compression; in the process of conversion, it once performs DV variable-length decoding and then performs MPEG variable-length encoding.
According to a seventh aspect, in the sixth aspect,
the compressing means further comprises filter means for converting the format of the digital video signal into a format in which the number of effective lines is 1080 lines for both of luminance and color difference and the number of horizontal effective samples is 1280 pixels for luminance and 640 pixels for color difference,
the macro block assembling means assembles 5400 macro blocks per frame from the digital video signal of the converted format without performing the process of increasing the number of effective lines, and
the recording means records the output signal of the compressing means on the recording medium in such a manner that one frame of the output signal is stored in 5400 fixed-length sync blocks on the recording medium.
In accordance with the seventh aspect, the format of the digital video signal is converted as stated above so that existing DV recording circuits can be used as the recording medium. This reduces the cost of the development of the digital video signal recording and reproducing device.
According to an eighth aspect, in the seventh aspect,
the recording means comprises,
four DV recording circuits provided in parallel each recording an input signal on the recording medium in such a manner that one frame of the input signal is stored in 1350 fixed-length sync blocks on the recording medium, and
distributing means for evenly distributing and outputting the output signal of the compressing means to the four DV recording circuits.
According to a ninth aspect, in the seventh aspect,
the recording means comprises,
two DV recording circuits provided in parallel each recording an input signal on the recording medium in such a manner that one frame of the input signal is stored in 2700 fixed-length sync blocks on the recording medium, and
distributing means for evenly distributing and outputting the output signal of the compressing means to the two DV recording circuits.
According to a tenth aspect, in the seventh aspect,
the digital video signal has a format in which the number of effective lines is 1080 lines for both of luminance and color difference and the number of horizontal effective samples is 1920 pixels for luminance and 960 pixels for color difference.
According to an eleventh aspect, in the second aspect,
the digital video signal recording and reproducing device further comprises decoding means for decoding the output signal of the reproducing means, wherein
the decoding means comprises reverse macro block assembling means for reversely assembling a signal equivalent to the digital video signal from the macro blocks assembled by the macro block assembling means.
In accordance with the eleventh aspect, the reproducing side can extract not only an MPEG stream but also a digital video signal.
According to a twelfth aspect, in the eleventh aspect,
the process of increasing the number of effective lines is a process of, when assembling macro blocks, adding a dummy line or dummy lines to a digital video signal in which the number of its effective lines is not a multiple of 16 to make the number of effective lines a multiple of 16,
the macro block reassembling means reassembles the macro blocks equivalent to those obtained by performing the process of increasing the number of lines by adding dummy blocks with 8 lines to the macro blocks assembled by the macro block assembling means, and
the reverse macro block assembling means reversely assembles the signal equivalent to the digital video signal by removing the dummy lines of 7 lines maximum from the macro blocks assembled by the macro block assembling means.
According to a thirteenth aspect, in the eleventh aspect,
the compressing means further comprises,
quantization means for quantizing an output signal of the DCT means according to the MPEG standard,
variable-length encoding means for variable-length encoding an output signal of the quantization means according to the MPEG standard, and
code rate control means for generating quantization information for controlling the code rate of the macro blocks assembled by the macro block assembling means so that N (N is an arbitrary natural number; which applies thereinafter) of the macro blocks can be exactly, without any remainder nor shortage, stored in N fixed-length sync blocks,
the converting means further comprises variable-length decoding means for variable-length decoding the output signal of the reproducing means according to the MPEG standard and outputting a signal obtained by this process to the macro block reassembling means and the decoding means,
the decoding means further comprises,
inverse quantization means for inversely quantizing the output signal of the variable-length decoding means according to the MPEG standard, and
inverse DCT means for applying inverse DCT to an output signal of the inverse quantization means according to the MPEG standard and outputting a signal obtained by this process to the reverse macro block assembling means, and
the code rate control means generates the quantization information on the basis of the output signal of the DCT means and provides the quantization information to the quantization means.
According to a fourteenth aspect, in the eleventh aspect,
the compressing means further comprises,
quantization means for quantizing an output signal of the DCT means according to the MPEG standard,
DV variable-length encoding means for variable-length encoding an output signal of the quantization means according to a DV standard, and
code rate control means for generating quantization information for controlling the code rate of the macro blocks assembled by the macro block assembling means so that N (N is an arbitrary natural number; which applies thereinafter) of the macro blocks can be exactly, without any reminder nor shortage, stored in N fixed-length sync blocks,
the converting means further comprises,
DV variable-length decoding means for variable-length decoding the output signal of the reproducing means according to the DV standard and outputting a signal obtained by this process to the macro block reassembling means and the decoding means, and
MPEG variable-length encoding means for variable-length encoding the output signal of the DV variable-length decoding means according to the MPEG standard,
the decoding means further comprises,
inverse quantization means for inversely quantizing the output signal of the DV variable-length decoding means according to the MPEG standard, and
inverse DCT means for applying inverse DCT to an output signal of the inverse quantization means according to the MPEG standard and outputting a signal obtained by this process to the reverse macro block assembling means, and
the code rate control means generates the quantization information on the basis of the output signal of the DCT means and provides the quantization information to the quantization means.
In accordance with the fourteenth aspect, the device performs DV variable-length encoding in the process of compression; in the process of conversion, it once performs DV variable-length decoding and then performs MPEG variable-length encoding.
According to a fifteenth aspect, in the fourteenth aspect,
the compressing means further comprises first filter means for converting the format of the digital video signal into a format in which the number of effective lines is 1080 lines for both of luminance and color difference and the number of horizontal effective samples is 1280 pixels for luminance and 640 pixels for color difference,
the macro block assembling means assembles 5400 macro blocks per frame from the digital video signal of the converted format without performing the process of increasing the number of effective lines,
the recording means records the output signal of the compressing means on the recording medium in such a manner that one frame of the signal is stored in 5400 fixed-length sync blocks on the recording medium, and
and wherein the decoding means further comprises second filter means for converting the format of an output signal of the reverse macro block assembling means into a format equivalent to that of the digital video signal.
In accordance with the fifteenth aspect, the format of the digital video signal is converted as explained above so that existing DV recording circuits can be used as the recording means. This reduces the cost of the development of the digital video signal recording and reproducing device.
According to a sixteenth aspect, in the fifteenth aspect,
the recording means comprises,
four DV recording circuits provided in parallel each recording an input signal on the recording medium in such a manner that one frame of the input signal is stored in 1350 fixed-length sync blocks on the recording medium, and
distributing means for evenly distributing and outputting the output signal of the compressing means to the four DV recording circuits.
According to a seventeenth aspect, in the fifteenth aspect,
the recording means comprises,
two DV recording circuits provided in parallel each recording an input signal on the recording medium in such a manner that one frame of the input signal is stored in 2700 fixed-length sync blocks on the recording medium, and
distributing means for evenly distributing and outputting the output signal of the compressing means to the two DV recording circuits.
According to an eighteenth aspect, in the fifteenth aspect, the digital video signal has a format in which the number of effective lines is 1080 lines for both of luminance and color difference and the number of horizontal effective samples is 1920 pixels for luminance and 960 pixels for color difference.
A nineteenth aspect is directed to a digital video signal transmission device for transmitting a digital video signal in which the remainder left when the number of its effective lines is divided by 16 is not less than 1 and not more than 8, the device comprising:
compressing means for compressing the digital video signal according to a procedure which partially differs from MPEG;
transmitting means for transmitting an output signal of the compressing means through a transmission medium in such a manner that one frame of the output signal is stored in a given number of fixed-length packets on the transmission medium; and
converting means for converting a signal transmitted through the transmission medium into an MPEG stream,
the compressing means comprising,
macro block assembling means for adding dummy lines of 7 lines maximum to the effective lines of the digital video signal and assembling macro blocks with 16 lines and macro blocks with 8 lines, and
DCT means for applying field DCT (Discrete Cosine Transform; which applies hereinafter) or frame DCT defined by the MPEG standard to the macro blocks with 16 lines and applying only the frame DCT defined by the MPEG standard to the macro blocks with 8 lines, and
the converting means comprising macro block reassembling means for reassembling the macro blocks assembled by the macro block assembling means into macro blocks which are equivalent to those obtained by performing the process of increasing the number of effective lines as defined by the MPEG standard.